ARCHITETTURA DEGLI ELABORATORI
Architettura degli Elaboratori
|Lecturer||Office hours for students|
|Alessandro Bogliolo||Monday, from 11:00 am to 12:00 am|
Assigned to the Degree Course
|Date||Time||Classroom / Location|
The course is aimed to describe a simple computer architecture, with emphasis on pipelining and memory hierarchy, by providing all the elements required to motivate design choices, understand the functioning, evaluate performance, and capture the relationship between architectural design choices and software programming techniques.
01.01 Automatic Information Processing.
01.02 Brief History of Computing.
02. Information Theory:
02.01 Digital Encodings.
02.02 Representation of Numerical Sets and Binary Arithmetic.
02.03 Representation of Non-Numerical Sets.
02.04 Special Encodings: Redundancy and Compression.
03. Logic Networks:
03.01 Boolean Algebra.
03.02 Switching Networks and Combinational Circuits.
03.03 Sequential Circuits.
03.04 Gate-Level Design.
03.05 Digital Systems.
03.06 Lab: Logic-Level Design and Simulation using TkGate.
03.07 Address Decoding.
04. Computer Systems:
04.01 Von-Neumann Bottleneck and CPU Micro-Architecture.
04.02 Istruction-Set Architecture.
05.01 Elementary Pipelining and Performance Metrics.
05.02 Reference Architecture: DLX.
05.03 Pipeline Hazards.
05.04 Lab: Cycle-Accurate Simulazione of DLX Pipeline using WonDLX/WinMIPS.
06. Performance Optimization:
06.01 Static Code Optimization.
06.02 Lab: Example of Simulation-Driven Static Code Optimization.
06.03 Multiple-Issue Processors.
06.04 Dynamic Optimization: OOO Execution and Speculation.
06.05 Lab: Development and Use of Performance Benchmarks.
07.01 Memory Devices: SRAM and DRAM.
07.02 Non-Volatile Memory Devices: ROM and Flash.
07.03 Memory Hierarchy: Caching and Virtual Memory.
08.01 BUS and I/O.
08.02 I/O Synchronization: Interrupts and DMA.
Although there are no mandatory prerequisites for this exam, students are strongly recommended to take it after Procedural and Logic Programming.
It is also worth noticing that the topics covered by this course will be used in Databases and Operating Systems.
Teaching, Attendance, Course Books and Assessment
Theory lectures and laboratory exercises, both face-to-face and on-line.
Although recommended, course attendance is not mandatory.
- Course books
Hennessy, Patterson, "Computer Organization and Design: The Hardware/Software Interface", 5th edition, Elsevier (Morgan Kauffman Series), 2013. [http://store.elsevier.com/product.jsp?isbn=9780123747501] (The IV edition is available online on Google books isbn 978-0-12-374750-1)
Hennessy, Patterson, "Struttura e progetto dei calcolatori: L'interfaccia hardware-software", Zanichelli, 2010.
Individual project, written exam and (optional) oral exam.
The individual project, which has to be submitted at least three days before the oral exam, is passed if the mark (which is valid for all the exam calls of the same Academic Year) is at least 18/30.
The written exam is passed if the mark (which is valid for all the exam calls of the same Academic Year) is at least 18/30.
The oral exam, which can be taken only if the project and the written exam have been passed, determines a spread between -5/30 and 5/30 of the average of the two previous marks, thus yielding the final mark.
There are no limitations to the number of trials per session per year.
The individual project and the written exam can be taken in any order.
If a student decides to take the written exam more than ones before taking the oral exam, the mark of the last trial is the one used to compute the final mark.
The course is offered both face-to-face and on-line within the Laurea Degree Program in Applied Computer Science.
For additional lecture notes and information visit http://informatica.uniurb.it/en/learning-activities/program-of-study/carc-2013-2014/carc_supp/
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